The present invention relates to a technique for testing a nonvolatile memory device which can electrically write and erase storing information and more specifically to a technique which can be effectively applied for shortening of the time required for the test, for example, a technique which can be effectively applied to a flash memory.
A flash memory utilizes a nonvolatile memory element, into a memory cell, consisting of a MOSFET of a double-gate structure including a control gate and a floating gate. This flash memory is capable of storing information by changing a threshold voltage of the MOSFET depending on change of the amount of charges accumulated in the floating gate.
In such flash memory, a threshold voltage changes in various manners due to the write or erase processes to a memory cell and normal write or erase process sometimes becomes impossible, for example, due to a fault such as fail of insulation film of MOSFET which forms a memory cell. In other words, a threshold voltage does not change in some cases even when the write or erase process is executed.
In the case of performing the write process in unit of memory cells (hereinafter, referred to as a sector) connected to only one word line, a flash memory has been placed under the control as a means in response to fluctuation of characteristics of memory cells that the write process is conducted through division into a plurality of write processes and a write voltage is never applied from the memory cells which have reached the predetermined threshold voltage. Moreover, the conventional flash memory has also been placed under the control that existence of fail bit is detected by a test of wafer level with a tester and management is also executed in unit of a sector, a sector including a fail bit is defined as a defective sector and information to discriminate fail and pass is stored in the sector management area and thereby the defective sector is never selected under the usual using condition by utilizing this management information.
For the test to detect a write fail bit or an erase fail bit, a test system is introduced to enhance the test efficiency in which the test of a plurality of chips is executed in parallel by bring the probe of tester into contact with a plurality of chips in the wafer condition.
As explained above, a method for simultaneously testing a plurality of chips in the wafer condition is certainly effective for an ordinary semiconductor integrated circuit. However, in the case of a flash memory, since the write process, for example, is conducted in a plurality of times of the write process as explained above, if a fail bit exists, in other words, a bit which does not or almost does not change its threshold voltage exists in the sector selected by a certain chip, the write process is ended using a longer period due to the existence of such fail bit and transfer to the next sector is not yet started during such period even when the write process of the present sector is completed in the other chips in which the sectors are normal.
Namely, the conventional tester which can simultaneously test a plurality of chips in the wafer condition is capable of moving a probe for each chip and therefore the testing time thereof is controlled depending on a chip including a fail sector. Therefore, such tester has a problem that the number of chips to be tested simultaneously cannot be increased too much because there is a fear that if the number of chips for simultaneous test is increased, probability that the selected sectors of a certain chip are fail sectors becomes high and thereby the testing time becomes longer. As explained above, in the existing flash memory and a method of testing the same, a test requires a higher cost because a longer time is required for the test and such higher testing cost has been considered as a factor which disables reduction in cost of chip.
It is therefore an object of the present invention to provide a testing technique which can shorten the testing time and thereby can reduce a unit price of chip in a nonvolatile semiconductor memory device which can realize electrical write or erase processes such as a flash memory.
The aforementioned and the novel characteristics of the present invention will become apparent from the description of the present specification and the accompanying drawings.
Typical ones of the inventions disclosed in the present specification will be explained as follows.
Namely, the first invention of the present specification provides a nonvolatile semiconductor memory device such as a flash memory comprising: a counter circuit for counting the number of fails generated in the write and erase processes in the predetermined unit like a sector; and a comparing circuit for judging whether a value counted by the counter circuit has exceeded a limit value (allowable value) of the preset number of fails or not so that when a counted value of the counter circuit has exceeded the preset limit value of a register, the writer or erase process is not conducted even if a write or erase command is inputted from an external circuit.
According to the means explained above, if the number of fail sectors has exceeded the limit value in any memory among a plurality of memories to be tested simultaneously, the write or erase process is not executed even if the write or erase command is inputted from an external circuit. Therefore, the test of the relevant chip is completed when the number of fail sectors has exceeded the limit value and thereafter this memory can prevent elongation of the write time or erase time and can shorten the total testing time.
Moreover, the other invention disclosed in the present specification provides a nonvolatile semiconductor memory device such as a flash memory having a structure that a storage area (pass/fail flag) for storing generation of a fail in the write and erase process in the predetermined unit such as a sector is provided and when information indicating generation of a fail is stored in the storage area, the write or erase process is not executed in the test mode for the corresponding sector within the memory array. Thereby, it is now possible that the write or erase process can be stopped for the sector for which the information indicating generation of fail is stored in the corresponding storage area by checking the storage area in the second and subsequent tests and the total testing time can be shortened.
The other invention disclosed in the present specification provides a nonvolatile semiconductor memory device comprising a memory array including a nonvolatile memory element which is provided with a control gate and a floating gate to store information through change of the threshold voltage. This nonvolatile semiconductor memory device has a structure to perform the read process for verification during the test operation in the level which is relatively lower than the level for the read process for verification under the usual operating condition and also to complete the relevant write or erase process when it is judged that a fail is generated in the write or erase process with the read process for verification during the test operation under the lower level explained above.
Accordingly, on the occasion of performing the write or erase process by repeating the applications of a write voltage or an erase voltage, when a threshold voltage does not change exceeding the predetermined level even if the initial write voltage or erase voltage is applied, the write or erase process can be completed upon judgment that a fail bit is included. As a result, repetition of useless process can be prevented and thereby a total testing time can be shortened.